1. Field of the Invention
The present invention relates to a crossbar circuit.
2. Description of the Related Art
One example of a conventional crossbar is disclosed in FIG. 1 of Unexamined Japanese Patent Application KOKAI Publication No. H11-212927. According to the crossbar disclosed in this publication, if the number of inputs increases, the structure of the crossbar become complicated and wiring delay and logical delay become larger, resulting in that the time required for processing is increased.
To solve this problem, the inventor of the present invention has got an idea that registers for retaining a data piece and an arbitration result generated by an arbiter should be provided on a data path and a path through which the arbitration result flows. A block diagram representing a data exchange system employing a crossbar 440 having this structure is shown in FIG. 9.
As shown in FIG. 9, this data exchange system comprises requesters 400 and 410, and the crossbar 440.
The requester 400 includes an output data register 401, an output control circuit 402, and a request register 403, and outputs a data piece and a request to the crossbar 440. The output control circuit 402 receives selection signals from selection registers 423 and 433 of the crossbar 440. In a case where the received selection signal represents that xe2x80x9ca preceding data piece has been allowed to be output to a crossbar output port OP0 or OP1xe2x80x9d, the output control circuit 402 sets a following data piece in the output data output control circuit 402 sets a following data piece in the output data register 401, and sets a request corresponding to the following data in the request register 403. The output data register 401 outputs the data piece set therein to a relay register 425, and the request register 403 outputs the request set therein to a request decoder 421.
The requester 410 has the same structure and functions as those of the requester 400, and is connected to another input port of the crossbar 440.
The crossbar 440 comprises crossbar output data registers 450 and 451, selectors 424 and 434, arbiters 422 and 432, selection registers 423 and 433 for retaining arbitration results of the arbiters 422 and 432 respectively, and relay registers 425 and 435 for retaining data pieces.
The request decoders 421 and 431 converts requests (information (request information) for specifying the requester, output destination, priority, etc.) input from the requester 400 and the requester 410 respectively, into request signals, and outputs the request signals to either of the arbiter 422 and the arbiter 423 that corresponds to the crossbar output port designated in the requests. The arbiters 422 and 432 arbitrate the requests input from the requesters 400 and 410 in accordance with the supplied request signals, and output a selection signal representing an arbitration result to the selection register 423 or the selection register 433. The selection registers 423 and 433 supply the selection signal to the selectors 424 and 434 respectively, and to the requesters 400 and 410 respectively. The relay registers 425 and 435 retain data pieces input by the requesters 400 and 410 to the crossbar 440. Each of the relay registers 425 and 435 outputs the retained data piece to the selectors 424 and 434. The selectors 424 and 434 select one of the two data pieces supplied thereto in accordance with the selection signal output from the selection register 423 or 433, and set the selected data piece in the crossbar output data registers 450 and 451 respectively. The crossbar output data registers 450 and 451 output the set data to the crossbar output ports OP0 and OP1.
An operation clock is supplied to each component described above, so that the components can operate synchronously. For example, the output data registers 401 and 411, the request registers 403 and 413, the relay registers 425 and 435, the selection registers 423 and 433, and the crossbar output data registers 450 and 451 retain an input data piece in response to a rise of a clock signal, and outputs a retained data piece in response to a fall of a clock signal.
Next, an operation of this system will be explained with reference to timing charts shown in FIG. 10A to FIG. 10F, by employing a case where the requester 400 outputs data pieces D1, D2, D3, . . . successively to the crossbar output port OP0, as an example. Note that it is assumed as a premise that an operation clock shown in FIG. 10F is supplied to each component.
First, the output data register 401 of the requester 400 outputs a data piece D1 to the relay register 425 at the timing T1 in accordance with the operation clock, as shown in FIG. 10B. The relay register 425 outputs the data piece D1 at the timing T2 in accordance with the next operation clock, as shown in FIG. 10D.
In the meantime, the request register 403 outputs request information corresponding to the data piece D1 at the timing T1. The arbiter 422 arbitrates the output request, and sends a selection signal representing an arbitration result to the selection register 423.
The selection register 423 outputs the selection signal for causing the data piece D1 to be output, at the timing T2 in response to the next operation clock, as shown in FIG. 10D. The selector 424 selects and outputs a data piece supplied from either one of the relay registers 425 and 435 in accordance with the selection signal (in this example, the selector 424 selects the data piece D1 from the relay register 425).
The relay register 425 outputs the data piece D1 at the timing T2 in accordance with the next operation clock, as shown in FIG. 10D. At the same timing, the selection register 423 outputs the selection signal (grant signal) to the selector 424 and to the output control circuit 402, as shown in FIG. 10A. The selector 424 transfers the data piece output from the relay register 425 to the crossbar output data register 450.
The selection signal is also supplied to the output control circuit 402. Thereby, the output control circuit 402 sets a data piece D2 in the output data register 401 and sets request information corresponding to the data piece D2 in the request register 403 at the timing T2. The data piece D2 and the corresponding request information will be output at the timing T3.
The same operation will be repeated for the following data pieces. As described, according to this system, even though the data pieces can be successively output from the crossbar 440 without being stopped at the requester 400 due to an arbitration result, a dead cycle amounting to 1T (=1 clock cycle) is produced between the timing at which the requester 400 or 410 outputs a preceding data piece and the timing at which the requester 400 or 410 outputs the next data piece.
Suppose that a following data piece is to be set in the output data register 401 at the same timing at which a preceding data piece is output to the relay register 425, in order to prevent the dead cycle from being produced. In this case, if the data pieces should be output successively and if the preceding data piece is stopped for a while from being output due to an arbitration result, the request information corresponding to the preceding data piece can not be saved from disappearing since the request information corresponding to the following data piece will be written upon the request information corresponding to the preceding data piece.
The crossbar having the structure described so far, needs to receive input of a next data piece and a request corresponding to the next data piece at a timing at which a preceding data piece is output therefrom or at a timing thereafter, in order to prevent disappearance of the request information of the data piece. As a result, the latency is long and the throughput is low.
The present invention was made in view of the above described problem, and an object of the present invention is therefore to provide a crossbar having registers provided on a data path through which a data piece flows and on an arbitration path through which an arbitration result flows, and thus achieving a shorter latency.
Another object of the present invention is to provide a crossbar having a high throughput.
To achieve the above objects, a crossbar circuit according to a first aspect of the present invention is a crossbar circuit comprising: i (i being a natural number equal to or greater than 2) number of requesters; and a crossbar which receives from the i number of requesters, an output data piece and request information including information representing that the output data piece is requested to be output from a desired output port among k (k being a natural number) number of output ports included in the crossbar, and which outputs the received output data piece to the desired output port, wherein:
each of the requesters includes an output data register from which the output data piece is output, j (j being a natural number equal to or greater than 2) number of request information registers from which the request information is output, and an output control circuit;
the crossbar includes
i number of data input ports which are arranged in one to one correspondence to the i number of requesters,
i number of request information input circuits which are arranged in one to one correspondence to the i number of requesters, and which each have j number of request information input ports for receiving the request information from the requesters,
i number of relay circuits which are connected to the i number of data input ports respectively, and which retain a data piece input thereto,
i number of first selection circuits which are arranged in one to one correspondence to the i number of request information input circuits, and which select any of j number of request information supplied from a corresponding one of the request information input circuits in accordance with a selection control signal retained by themselves,
k number of arbiters which are arranged in one to one correspondence to the k number of output ports, and which each arbitrate requests represented by the j number of request information output from the i number of first selection circuits, and output an arbitration result signal,
k number of selection registers which are arranged in one to one correspondence to the k number of arbiters, and which retain the arbitration result signal output from a corresponding one of the arbiters,
k number of second selection circuits which are arranged in one to one correspondence to the k number of selection registers, and which receive the arbitration result signal from a corresponding one of the selection registers, receive output data pieces from the i number of relay circuits, select any one of the received output data pieces in accordance with the received arbitration result signal, and output the selected output data piece to the output port associated with themselves in one to one correspondence, and
i number of request selection control circuits which are arranged in one to one correspondence to the i number of relay circuits, and which receive the arbitration result signals output from the k number of arbiters, updates the selection control signal based on the arbitration result signals, and supplies the selection control signal to the first selection circuits; and
the output control circuit is a circuit which receives the arbitration result signal from the crossbar, controls the output data register to output an output data piece retained therein to the crossbar in a case where the received arbitration result signal represents that the output data piece which had been output from the requester in which the output control circuit itself is included is selected to be output from the crossbar, sets an output data piece to be output next in the output data register, and sets request information corresponding to the output data piece to be output next in another request information register without changing the content of the request information register in which the request information corresponding to the output data piece which has just been output is stored.
The crossbar may further include i number of decoding circuits which are arranged in one to one correspondence to the i number of first selection circuits, and which convert the request information to the request and send the request to the desired output port which is designated by the request information.
Each of the arbiters may arbitrate requests output from the i number of decoding circuits, and output the arbitration result signal.
The first selection circuits may select the request information input ports cyclically in accordance with the selection control signal retained by themselves to select the j number of request information.
The output control circuit may cyclically select the request information registers in which request information corresponding to an output data piece to be output next is set.
The crossbar may further include:
k number of request output ports; and
k number of third selection circuits which are arranged in one to one correspondence to the k number of selection registers, and which each receive the arbitration result signal from a corresponding one of the selection registers, select any of request information selected by the i number of first selection circuits, and output the selected request information to the request output ports associated with themselves in one to one correspondence.
In the crossbar, each of the i number of relay circuits may be a circuit which is constituted by m (m being a natural number) number of registers.
The crossbar circuit may operate synchronously with a clock signal, which is generated periodically.
To achieve the above objects, a crossbar circuit according to a second aspect of the present invention is a crossbar circuit comprising: i (i being a natural number equal to or greater than 2) number of requesters; and a crossbar which receives from the i number of requesters, an output data piece and request information including information representing that the output data piece is requested to be output from a desired output port among k (k being a natural number) number of output ports included in the crossbar, and which outputs the received output data piece to the desired output port, wherein:
each of the requesters includes an output data register from which the output data piece is output, j (j being a natural number equal to or greater than 2) number of request information registers from which the request information is output, and an output control circuit; and
the crossbar includes
i number of data input ports which are arranged in one to one correspondence to the i number of requesters,
i number of request information input circuits which are arranged in one to one correspondence to the i number of requesters, and which each have j number of request information input ports for receiving the request information from the requesters,
i number of relay circuits which are connected to the i number of data input ports respectively, and which retain a data piece input thereto,
i number of first selection circuits which are arranged in one to one correspondence to the i number of request information input circuits, and which select any of j number of request information supplied from a corresponding one of the request information input circuits in accordance with a selection control signal retained by themselves,
k number of arbiters which are arranged in one to one correspondence to the k number of output ports, and which each arbitrate requests represented by the j number of request information output from the i number of first selection circuits, and output an arbitration result signal,
k number of selection registers which are arranged in one to one correspondence to the k number of arbiters, and which retain the arbitration result signal output from a corresponding one of the arbiters,
k number of second selection circuits which are arranged in one to one correspondence to the k number of selection registers, and which receive the arbitration result signal from a corresponding one of the selection registers, receive output data pieces from the i number of relay circuits, select any one of the received output data pieces in accordance with the received arbitration result signal, and output the selected output data piece to the output port associated with themselves in one to one correspondence,
i number of request selection control circuits which are arranged in one to one correspondence to the i number of relay circuits, and which receive the arbitration result signals output from the k number of arbiters, updates the selection control signal based on the arbitration result signals, and supplies the selection control signal to the first selection circuits, and
i number of circuits which are arranged in one to one correspondence to the i number of requesters, and which supply the arbitration result signal to the requesters in order to cause the requesters to control outputting of the output data piece and outputting of the request information.
The crossbar may further include i number of decoding circuits which are arranged in one to one correspondence to the i number of first selection circuits, and which convert the request information to the request and send the request to the desired output port which is designated by the request information.
Each of the arbiters may arbitrate requests output from the i number of decoding circuits, and output the arbitration result signal.
The crossbar may farther include k number of output data registers, which are arranged in one to one correspondence to the k number of second selection circuits, and which retain an output data piece output from a corresponding one of the second selection circuit, and output the retained output data piece to the output port associated with themselves in one to one correspondence.
The k number of second selection circuits may be circuits which are arranged in one to one correspondence to the k number of selection registers, and which receive the arbitration result signal from a corresponding one of the selection registers, receive output data pieces from the i number of relay circuits, select any one of the received output data pieces in accordance with the received arbitration result signal, and output the selected output data piece to the output data registers.
The first selection circuits may select the request information input ports cyclically in accordance with the selection control signal retained by themselves to select the j number of request information.
The output control circuit may cyclically select the request information registers in which request information corresponding to an output data piece to be output next is set.
The crossbar may further include:
k number of request output ports; and
k number of third selection circuits which are arranged in one to one correspondence to the k number of selection registers, and which each receive the arbitration result signal from a corresponding one of the selection registers, select any of request information selected by the i number of first selection circuits, and output the selected request information to the request output ports associated with themselves in one to one correspondence.
The crossbar may further include request relay registers which are arranged between the first selection circuits and the third selection circuits, and which retain and output request information selected by the first selection circuits.
The crossbar may further include k number of request output registers which are arranged in one to one correspondence to the k number of third selection circuits, and which retain request information output from a corresponding one of the third selection circuits and output the request information to the request output ports associated with themselves in one to one correspondence.
The k number of third selection circuits may be circuits which are arranged in one to one correspondence to the k number of selection registers, and which receive the arbitration result signal from a corresponding one of the selection registers, receive output data pieces from the i number of relay registers, select any of the received output data pieces in accordance with the received arbitration result signal, and output the selected output data piece to the request output registers.
In the crossbar, each of the i number of relay circuits may be a circuit which is constituted by m (m being a natural number) number of registers.
In the crossbar, there may be a relationship m less than k, between the value m and the value k.
The crossbar circuit may operate synchronously with a clock signal, which is generated periodically.
In the crossbar circuit, there may be a relationship k greater than n, between the value k and a value n which represents a number of clock cycles needed from a timing at which request information is selected by the i number of first selection circuits to a timing at which the arbitration result signal is set in the k number of selection registers.